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NPKT offers full custom layout solutions based on Takumi Technology tools.
NPKT flows operate on layout based on GUIs or config files, standalone, or embedded in 3rd party systems such as Cadence Virtuoso. Layout engines are used through the Takumi Tools API in C++ or Python scripting language.
DRC-fix and migration
DRC-fix repairs errors in layout, for any process technology, including 22 and 28nm nodes, which have many conditions and gridding requirements. DRC-fix can be used for layout migration or for creating layout derivatives (e.g. std.cell libraries with modified device size and different number of routing tracks).
DRC-fix works flat or hierarchical, is fully 2D and dynamic for correct handling of width-dependent space rules, end-of-line rules and others. DRC-fix can work in batch on GDS or OASIS, or can be integrated in Virtuoso for pCell maintenance and interactive use.
Preferred rule & yield score improvement
All current manufacturing processes have minimum and recommended design rules, when implemented improve yield score and manufacturability.
Product tkenhance will implement rule preferences, without increasing cell size, and while keeping layout DRC and LVS correct. Tkenhance has been used for cell libraries, embedded memories, analog blocks as well as full chips.
Litho hotspot solving and analysis
Litho hotspots reduce yield mainly in defocus or misalignment conditions. While most hotspots in early stages of process development get fixed by improved OPC decks it makes sense to (automatically) remove hotspots for reduced yield risk.
Our tools will fix hotspots in cell libraries, IP blocks or full chips based on hotspot markers, or imported contours from e.g. commercial tools such as Brion or Calibre LFD. For large data, hotspot fix uses hierarchy analysis and/or layout partitioning over multiple cpus, to provide fast turnaround time.
Time-dependent dielectric breakdown (TDDB) analysis
Dielectric material in between SOC signal wires can break down due to prolonged exposure to stress due to voltage differences across the wires.
TDDB analysis reads chip layout from DEF, and voltage information from your power domain definition, and plots for all metals and via’s the distribution of voltage difference per space range. This allows you to find voltage hotspots, and therefore reliability risks, on your chip.
Application development service
For urgent and/or non-standard analysis methods, NPKT offers application development services.
